1. Field of the Invention
The present invention relates to computer systems and specifically to accessing memory in a computer system.
2. Background Information
Computer architecture generally defines the functional operation, including the flow of information and control, among individual hardware units of a computer. One such hardware unit is the processor or processing engine, which contains arithmetic and logic processing circuits organized as a set of data paths. In some implementations, the data path circuits may be configured as a central processing unit (CPU) having operations that are defined by a set of instructions. The instructions are typically stored in an instruction memory and specify a set of hardware functions that are available on the CPU.
A high-performance computer may be realized by using a number of CPUs or processors to perform certain tasks in parallel. For a purely parallel multiprocessor architecture, each processor may have shared or private access to resources, such as program instructions (e.g., algorithms) or data structures stored in a memory coupled to the processors. Access to the memory is generally handled by a memory management unit (MMU), which accepts memory requests from the various processors and processes them in an order that often is controlled by logic contained in the MMU. Moreover, certain complex multiprocessor systems may employ many MMUs where each memory is associated with its own MMU and the processor is coupled to the memory through its MMU.
In these multiprocessing systems, each processor may need to access data contained in the various memories. One way to accommodate this is to couple each processor to each memory in a fully-meshed crossbar arrangement such that each processor is directly coupled to each memory through its MMU. However, depending on the system and implementation this approach may not be desirable as the number of connections required may be quite numerous and in some cases impractical. For example, a system comprised of sixteen processors and four memories may require 64×2×N connections, where “N” is the width of the bus, in order to accommodate separate read and write bus connections between each processor and memory. In a typical multiprocessor system N is usually some number greater than 32; thus, the number of connections would be 4096 or greater. In some implementations, such as where the multiprocessor systems are contained in a single Application Specific Integrated Circuit (ASIC), such a large number of connections may not be practical.